1. Field of the Invention
The present invention relates to the field of semiconductor devices and methods of manufacture thereof.
2. Description of Related Art
In general, gate structures of many semiconductor devices employ multiple layer gate and interconnect materials which maintain the properties of polycrystalline silicon but add a high-conductivity layer on top. For example, polysilicon and tungsten-silicide layers (WSix) are commonly used for this purpose. That is, semiconductor devices that employ polycrystalline silicon (polysilicon) gates formed over a gate dielectric layer encounter increased resistance of the polysilicon as size is scaled down to achieve higher circuit density. Due to the resulting relatively high resistance values of the polysilicon layer, a tungsten silicide (WSix) layer is often formed in order to lower resistance along the polysilicon gate. Generally, the ratio of silicon to tungsten is approximately 2.6 to 1 within the tungsten silicide (WSix) layer. Initially, problems emerged with adhesion of the metal silicide to the polysilicon.
One method for making semiconductor devices of higher density and improved performance is disclosed by McPherson (U.S. Pat. No. 4,816,425). McPherson teaches a semiconductor device having a gate 11 comprising a multi-layer structure including a layer 11a of polycrystalline silicon with an overlying layer of refractory metal silicide 11b, such as MoSi2 or Wsi2. In McPherson, the problem of adhesion of the metal silicide to the polysilicon is addressed by forming a thin silicon oxide coating 11c on the polysilicon before sputtering the metal silicide layer. The resulting multi-layer structure has low resistance but retains the advantages of polysilicon on silicon.
Chung (U.S. Pat. No. 5,646,070) teaches a single process for creating a multi-layered semiconductor device that employs tungsten silicide but incorporates an intervening layer that prevents degradation of the electrical properties of the underlying silicide during the fabrication process. Since CVD-tungsten involves fluorine chemistry, such a protective layer prevents the interaction during fabrication of the vapor deposited by CVD-tungsten with the underlying silicide.
Neither of these multi-layer methods addresses modifying the WSix layer itself to increase device density or speed. Further reducing semiconductor dimensions while maintaining or increasing performance is an on-going objective of semiconductor device design. Because of the large number of gates employed in semiconductor devices, a reduction in gate size can result in a substantial reduction in the overall dimensions of the semiconductor device accompanied by increased device density and even increased device speed.
The shrinkage of gate dimension increases resistivity and decreases speed. There are two usual approaches for decreasing resistivity. The first approach decreases the x-ratio, and the second approach increases the thickness of WSix. However, these two approaches increase the grain size of WSix and result in a rough surface. In particular, a decrease in x-ratio from x=2.3 to x=2.1 actually increases WSix grain size after anneal. This increase in WSix grain size results in increased surface roughness. Also, increased thin film grain size results in increased side-wall roughness after gate conductor (GC) etching as well as increased likelihood of gate conductor side-wall extension, thereby reducing realizable device density. The lowering of the x-ratio is not feasible as an approach to achieving a decrease in WSix thickness, because of these undesirable increases in surface and side-wall roughness.
The conventional .structure of (WSix) film employed in semiconductor devices is a single layer. After the anneal step of a typical semiconductor thin film fabrication process employing a single WSix layer, WSix grains grow larger and aggregate in a single grain layer with the grain boundary reaching to the Poly/WSix and WSix/SiN interfaces. These larger grains introduce a WSix surface with significant roughness, which results in semiconductor devices with reduced gate density. The roughness after anneal of a prior art WSix film with x-ratio of 2.59 and with a thickness of THK=568.6 nm is unacceptable.
The present invention provides a method of preparing small grain size WSix structures in general, and in particular, of preparing gate conductors.
The present invention provides a method of decreasing resistivity but preventing larger grain size by introducing a multilayer structure of WSix.
More particularly, the present invention is directed to a method for manufacturing a WSix film with smaller grains by providing a multi-layer WSix structure. The WSix film is prepared with smaller grains after anneal by introducing a multi-layer WSix structure prior to anneal. Instead of the single WSix layer of the prior art, the present invention introduces a multi-layer WSix structure at deposition, so that a multi-layer WSix grain structure with each layer having a smaller and more uniform grain size results after anneal.